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AS8202NF ttp-c2nf communication controller data sheet www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 1 - 20 1 general description the AS8202NF communication controller is an integrated device supporting serial communication according to the ttp specif ication version 1.1. it performs all communication tasks such as reception and transmission of messages in a ttp cluster without interaction of the host cpu. ttp provides mechanisms that allow the deployment in high-dependability distributed real-time system s. it provides the following services: predictable transmission of messages with minimal jitter fault-tolerant distributed clock synchronization consistent membership se rvice with small delay masking of single faults 2 key features dual-channel controller for redundant data transfers dedicated controller supporting ttp (time-triggered protocol class c) suited for dependable distributed real-time systems with guaranteed response time asynchronous data rate up to 5 mbit/s (mfm/ manchester) synchronous data rate 5 to 25 mbit/s bus interface (speed, encoding) for each channel selectable independently 40 mhz main clock with su pport for 10 mhz crystal, 10 mhz oscillator or 40 mhz oscillator 16 mhz bus guardian clock with support for 16 mhz crystal or 16 mhz oscillator single power supply 3.3v, 0.35m cmos process full automotive temperature range (-40oc to 125oc) 16k x 16 sram for message , status, control area (communication network interface) and for scheduling information (medl) 4k x 16 (plus parity) instruction code ram for protocol execution code data sheet conforms to protocol revision 2.04 16k x 16 instruction code rom containing startup execution code and deprecated protocol code revision 1.00 16 bit non-multiplexed asynchronous host cpu interface 16 bit risc architecture software tools, design support, development boards available ( www.tttech.com ) certification support package according to rtca/ do-254 dal a available ( www.tttech.com ) 80 pin lqfp80 package 3 applications application fields: automotive (by-wire braking, steering, vehicle dynamics control, drive train control), aerospace (aircraft electronic systems), industrial systems, railway systems. figure 1. block diagram d[15:0] a[11:0] ceb oeb web readyb intb led[2:0] ram_clk_testse use_ram_clk xin0 xout0 plloff resetb quartz or oscillator host processor interface rxd[1:0] rxclk[1:0] rxdv[1:0] rxer[1:0] xin1 xout1 txd[1:0] cts[1:0] txclk[1:0] ram_clk_testse ftest stest fidis ttest te s t interface ttp bus media drivers communication network interface (cni) ttp protocol processor core instruction memory ram & rom te s t interface transmitter bus guardian receiver AS8202NF
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 2 - 20 AS8202NF ttp-c2nf data sheet - applications contents 1 general description ............................................................................................................ ................... 1 2 key features ............................................................................................................................... ............ 1 3 applications ................................................................................................................... ......................... 1 4 pin assignments ................................................................................................................ .................... 3 4.1 pin descriptions ........................ ....................................................................................... ................................. 3 5 absolute maximum ratings ......... .............................................................................................. ........... 6 6 electrical characteristics..................................................................................................... .................. 7 7 detailed description ........................................................................................................... .................... 9 7.1 host cpu interface ............................................................................................................................... ............ 9 7.1.1 synchronous readyb generation.................. .............. .............. ............ ........... ........... ........... ............12 7.2 reset and oscillator .... .............. .............. .............. .............. .............. ........... ........... ........... ............................. 13 7.2.1 external reset signal............................... .................................................................... .........................13 7.2.2 integrated power-on reset ........................... .................................................................... ...................13 7.2.3 oscillator circuitry .................................................................................................... .............................13 7.2.4 build-up characteristics ................................................................................................ ........................14 7.3 ttp bus interface .............................................................................................................. ............................. 15 7.4 ttp asynchronous bus interface...... .............. .............. .............. .............. .............. ........... .......... ................... 15 7.5 ttp synchronous bus interface .................................................................................................. ................... 16 7.6 test interface ................................................................................................................. .................................. 16 7.7 led signals.................................................................................................................... ................................. 17 8 package drawings and markings.................................................................................................. ...... 18 9 ordering information........................................................................................................... ................. 19
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 3 - 20 AS8202NF ttp-c2nf data sheet - pin assignments 4 pin assignments figure 2. pin assignments lqfp80 package pin descriptions table 1. pin descriptions pin name pin number dir description v dd 12,29,49,59, 74 p positive power supply v ss 13,30,41,50, 60,75 p negative power supply v ddbg 70 p positive power supply for bus guardian (connect to v dd ) v ssbg 73 p negative power supply for bus guardian (connect to v ss ) v ddpll 4 p positive power supply for main clock pll (connect to v dd ) v sspll 80 p negative power supply for main clock pll (connect to v ss ) ram_clk_t estse 21 i pd ram_clk when stest=0 and use_ram_clk=1, else test input, connect to v ss if not used stest 22 i pd test input, connect to v ss ftest 24 i pd test input, connect to v ss fidis 25 i pd test input, connect to v ss ttest 61 i pu test input, connect to v dd use_ram_c lk 34 i pd ram_clk pin enable, connect to v ss if not used ceb vss vddbg d15 d14 d13 d12 readyb xin1 vssbg web oeb d11 d10 d9 d8 vdd ttest vsspll xout1 vss vdd a3 a4 vss fidis xin0 nc xout0 txd0 vddpll cts0 rxer0 txclk0 rxclk0 rxd0 rxdv0 vdd txd1 vss cts1 rxer1 txclk1 rxclk1 rxd1 rxdv1 d7 d5 d6 d4 d2 d3 d1 d0 vdd a10 a11 a9 a7 a8 a6 vss a5 resetb vss intb vdd nc led1 led2 led0 use_ram_clk nc a0 a1 a2 1 20 21 40 41 60 61 80 ftest plloff stest ram_clk_testse AS8202NF ttp communications controller (top view)
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 4 - 20 AS8202NF ttp-c2nf data sheet - pin assignments xin0 2 a main clock: analog cmos oscill ator input, use as input when providing external clock xout0 3 a main clock: analog cmos oscillator output, leave open when providing external clock plloff 23 i pd main clock pll disable pin, connect to v ss when providing 10 mhz crystal for enabling the internal pll xin1 72 a bus guardian clock: analog cmos oscillator input, use as input when providing external clock xout1 71 a bus guardian clock: analog cmos oscillator output, leave open when providing external clock resetb 26 i pu main reset input, active low txd0 5 o pu ttp bus channel 0: transmit data cts0 6 o pd ttp bus channel 0: transmit enable rxd0 11 i pu ttp bus channel 0: receive data txclk0 7 i pd ttp bus channel 0: transmit clock (mii mode) rxer0 8 i pu ttp bus channel 0: receive error (mii mode) rxclk0 9 i pd ttp bus channel 0: receive clock (mii mode) rxdv0 10 i pu ttp bus channel 0: receive data valid (mii mode) txd1 14 o pu ttp bus channel 1: transmit data cts1 15 o pd ttp bus channel 1: transmit enable rxd1 20 i pu ttp bus channel 1: receive data txclk1 16 i pd ttp bus channel 1: transmit clock (mii mode) rxer1 17 i pu ttp bus channel 1: receive error (mii mode) rxclk1 18 i pd ttp bus channel 1: receive clock (mii mode) rxdv1 19 i pu ttp bus channel 1: receive data valid (mii mode) a[11:0] 48-42, 39-35 i host interface (cni) address bus 1 d[15:0] 69-62, 58-51 i/o host interf ace (cni) data bus, tristate ceb 76 i pu host interface (cni) chip enable, active low oeb 77 i pu host interface (cni) output enable, active low web 78 i pu host interface (cni) write enable, active low readyb 79 o pu host interface (cni) transfer finish signal, active low, open drain 2 intb 28 o pu host interface (cni) time signal (interrupt), active low, open drain led[2:0] 33-31 o pd configurable generic output port nc 1, 27, 40 not connected, leave open 1. the device is addressed at 16-bit data word boundarie s. if the device is connected to a cpu with a byte- granular address bus, remember that a[11:0] of the as 8202nf device has to be connected to a[12:1] of the cpu (considering a little endian cpu address bus) 2. at de-assertion readyb is driven to the inactive value (high) for a configurable time. table 2. pin directions dir description i ttl input i pu ttl input with internal weak pull-up i pd ttl input with internal weak pull-down i/o ttl input/output with tristate o pu ttl output with internal weak pull-up at tristate table 1. pin descriptions pin name pin number dir description
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 5 - 20 AS8202NF ttp-c2nf data sheet - pin assignments o pd ttl output with internal weak pull-down at tristate a analog cmos pin ppower pin table 2. pin directions dir description
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 6 - 20 AS8202NF ttp-c2nf data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in section 6 electrical characteristics on page 7 is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units notes dc supply voltage (v dd )-0.35.0v input voltage (v in )-0.3v dd +0.3 v any pin input current (l in ) -100 100 ma any pin, t amb =25oc storage temperature (t strg ) -55 150 oc soldering temperature (t sold ) 235 oc t=10 sec, reflow and wave package body temperature (t body ) 240 oc 1 1. the reflow peak soldering temperatur e (body temperature) specified is in accordance with ipc/jedec j-std- 020c ?moisture/reflow sensitivity classification for n on-hermetic solid state surf ace mount devices?. the lead finish for packages is (85%/15% sn/pb). humidity (h) 5 85 % electrostatic discharge (esd) 1000 v hb m: 1kv mil.std.883, method 3015.7
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 7 - 20 AS8202NF ttp-c2nf data sheet - electrical characteristics 6 electrical characteristics t amb = -40 to +125 oc, v dd = 3v to +3.6v, v ss = 0v unless otherwise specified. table 4. electrical characteristics symbol parameter conditions min typ max units operating conditions i dds static supply current all inputs tied to v dd /v ss , clocks stopped, exclusive of i/o drive requirements, v dd =3.6v 5900a i dd operating supply current 1 v dd =3.3v, pll active, exclusive of i/o drive requirements 100 ma clk0_ ext _pll clock period of main clock (external) 1 pll active 2 100 ns clk0_ ext pll inactive 25 ns clk1 clock period of bus guardian clock 1 62.5 ns ttl input pins and ttl bidirectional pins in input/tristate model v il input low voltage 0.8 v v ih input high voltage 2.0 v i inleak input leakage current pins without pad resistors, v dd =3.6v -1 1 a i il input low current pins with pull- down resistors v dd =3.0v v in =0.4v 4.9 3 a v in =0.8v 8.8 3 pins with pull-up resistors v dd =3.6v v in =0v -15 -75 i ih input high current pins with pull- down resistors v dd =3.6v v in =3.6v 15 75 a pins with pull-up resistors v dd =3.0v v in =2.0v -10.7 3 v in =2.5v -6 3 c in input capacitance 4.5 4 pf rxd pin t asym_rx t(v in =0.5*v dd ) asymmetric receiver delay rxd t = 125 oc, v dd =3.0v, c load =35pf rxd[1,0] -2 4 2 4 ns cmos inputs (xin) , drive from external clock generator drive at xin (xout = open) c xin input capacitance 1.9 2.5 pf i xin input current 1 4 a v il_xin input low voltage 0 0.3* v dd v v ih_xin input high voltage 0.7* v dd v dd v
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 8 - 20 AS8202NF ttp-c2nf data sheet - electrical characteristics note: if min/max values are both negative, they ar e ordered according to their absolute value. outputs and ttl bidirectional pins in output mode i ol output low current v dd =3.0v, vo = 0.4v -4 ma i oh output high current v dd =3.0v, vo = 2.5v 4 ma i oz output tristate current v dd =3.6v 10 4 a t rise t(v out =0.1*v dd ) to t(v out =0.9*v dd ) transition time ? rise t = 125 oc, v dd =3.0v, c load =35pf cts[1,0], led[2:0], intb 8.1 3 ns d[15:0], readyb 8.9 3 t fall t(v out =0.9*v dd ) to t(v out =0.1*v dd ) transition time ? fall t = 125 oc, v dd =3.0v, c load =35pf cts[1,0], led[2:0], intb 6 3 ns d[15:0], readyb 7 3 txd pins t rise t(v out =0.3*v dd ) to t(v out =0.7*v dd ) transition time ? rise txd t = 125 oc, v dd =3.0v, c load =35pf txd[1,0] 4.5 4 ns t fall t(v out =0.7*v dd ) to t(v out =0.3*v dd ) transition time ? fall txd t = 125 oc, v dd =3.0v, c load =35pf txd[1,0] 3 4 ns t asym_rx t(v out =0.5*v dd ) asymmetric driver delay txd t = 125 oc, v dd =3.0v, c load =35pf txd[1,0] -3 4 3 4 ns 1. typical values: clk0=40 mhz, clk1=16 mhz 2. using the internal pll multiplies the main clock frequency by 4 3. implicitly tested. 4. guaranteed by design; not tested during production table 4. electrical characteristics symbol parameter conditions min typ max units
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 9 - 20 AS8202NF ttp-c2nf data sheet - detailed description 7 detailed description the AS8202NF is the first ttp controller to support bot h mfm and manchester coding. manchester coding is important for dc-free data transmission, which allows th e use of transformers in the data stream. the AS8202NF is pin-compatible with its predecessor, t he as8202. the AS8202NF provides support for fault-tolerant, high-speed bus systems in a single device. the communication controller is qualified for the full temperature range required for automotive applications and is certifiable according to rt ca standards. it offers superior reliability and supports data transfer rates of 25 mbit/s with mii and up to 5 mbit/s with mfm/manchester. the cni (communication network interface) forms a temporal firewall. it decouples the controller network from the host subsystem by use of a dual ported ram (cni). this prevent s the propagation of control errors. the interface to the host cpu is implemented as a 16-bit wide non-multiplexed asynchronous bus interface. the ttp follows a conflict-free media access strategy ca lled time division multiple access (tdma). this means, ttp deploys a time slot technique based on a global time that is permanently synchronized. each node is assigned a time slot in which it is allowed to perform transmit operation. the sequence of time slots is called tdma round, a set of tdma rounds forms a cluster cycle. the operation of the network is repeated after one cluste r cycle. the sequence of interactions forming the cluster cycle is defined in a static time schedule, called message descriptor list (medl). the definition of the medl in conjunction with the global time determines the response time for a service request. the membership of all nodes in the network is evaluated by the communications controller. this information is presented to all correct cluster members in a consistent fa shion. during operation, the st atus of all other nodes is propagated within one tdma round. please read more about ttp and request the ttp specification at www.tttech.com . host cpu interface the host cpu interface, also referred to as cni (communica tion network interface), connects the application circuitry to the AS8202NF ttp controller. all related signal pins provide an asynchronous read/write access to a dual ported ram located in the AS8202NF. there are no setup/hold co nstraints referring to the mi crotick (main clock ?clk0?). all accesses have to be executed on a granularity of 16 bit (2 byte), the device does not support byte-wide accesses. the pin a0 (lsb) of the device differentiates even and odd 16 bit word addresses and is typically connected to a1 of a little-endian host cpu. the a0 of host cpu is not connected to the device, and the application/driver on the host cpu should force all accesses to be 16 bit. for efficiency re asons, the host cpu application/driver may access some memory locations of the AS8202NF using wider accesses (e .g. 32 bit), and the bus interface of the host cpu will automatically split the access into two co nsecutive 16-bit wide accesses to the ttp controller. note that particularly in such a setup all timing parameters of th e host cpu interface must be met, especi ally the inactivity timeouts described as symbols 16?19. the host interface features an interrupt or time signal in tb to notify the application circuitry of programmed and protocol-specific, synchronous and asynchronous events. the host cpu interface allows access to the internal instru ction code memory. this is required for proper loading of the protocol execution code into the internal instruction code ram, for extensive testing of the instruction code ram and for verifying the instruction code rom contents. intb is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pull- up resistors or transistors may be necessary depending on the application. readyb is also an open-drain output, but with a possibility to be dr iven to ?1? for a defined time (selectable by register) before weak-pull-up at any other time. the led port is software-configurable to automatically show some protocol-related states and events, see below for the led port configuration. table 5. host interface ports pin name mode width comment a[11:0] in 12 cni address bus, 12 bit (a0 is lsb) d[15:0] inout (tri) 16 cni data bus, 16 bit (d0 is lsb) ceb in 1 cni chip enable, active low web in 1 cni write enable, active low
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 10 - 20 AS8202NF ttp-c2nf data sheet - detailed description asynchronous readyb permits the shortest possible bus cycle but ev entually requires signal synchronization in the application. connect use_ram_clk to v ss to enable this mode of operation. synchronous readyb uses an external clock (usually the host processor?s bus clock) for synchronization of the signal, eliminating external synchronization logic. connect use_ram_clk to v dd and ram_clk_testse to the host processor's bus clock to enable this mode of operation. note: due to possible metastability occurre nce, it is not recommended to be used in safety critical systems. oeb in 1 cni output enable, active low readyb out (open drain) 1 cni ready, active low intb out (open drain) 1 cni interrupt, time signal, active low ram_clk_testse in 1 host clock use_ram_clk in 1 host clock pin enable table 6. asynchronous dpram interface symbol parameter conditions min typ max units tc controller cycle time 25 ns 1a input valid to ceb, web (setup time) a[11:0] 5ns 2a d[15:0] 1b ceb, web to input invalid (hold time) a[11:0] 3 ns 2b d[15:0] 4 3 input rising to ceb, web falling ceb, web, oeb 5 1 ns 4 ceb, web rising to input falling ceb, web, oeb 5 1 ,2 ns 5 write access time (ceb, web to readyb) min = 1 tc, max = 4 tc 25 100 ns 6 ceb, web de-asserted to readyb de-asserted 9.4 ns 7a input valid to ceb, oeb (setup time) a[11:0] 5 ns 7b ceb, oeb to input invalid (hold time) a[11:0] 2 ns 8 input rising to ceb, oeb falling ceb, web, oeb 5 1 ns 9 ceb, oeb risin g to input falling ceb, web, oeb 5 1 ns 10 read access time (ceb, oeb to readyb) min = 1.5 tc, max = 8 tc 37.5 200 ns 11a ceb, oeb asserted to signal asserted d[15:0] 4.0 8.4 ns 11b ceb, oeb de-asserted to signal de-asserted d[15:0] 3.8 8 ns 11c readyb 8.8 12 readyb, d skew 2 ns 13 ram_clk_testse rising to readyb falling use_ram_clk=1 3.7 13.5 ns table 5. host interface ports pin name mode width comment
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 11 - 20 AS8202NF ttp-c2nf data sheet - detailed description note: all values not tested during pr oduction, guaranteed by design. figure 3. read/write access inactivity time 14 ram_clk_testse rising to readyb rising use_ram_clk=1 3 9.7 ns 15 ram_clk_testse rising to readyb deactivated 1->z use_ram_clk =1 ready delay='00' 3.6 12.9 ns ready delay=01 4.5 15.4 ready delay=10 5.4 18.8 ready delay=11 6.4 22.2 16 read to read access inactivity time (ceb, oeb low to ceb, oeb low) min = 1.5 tc 37.5 1 ns 17 read to write access inactivity time (ceb, oeb low to ceb, web low) 5 1 ns 18 write to write access inactivity time (ceb, web low to ceb, web low) 5 1 , 2 ns 19 write to read access inactivity time (ceb, web low to ceb, oeb low) 5 1 , 2 ns 1. prior to starting a read or write access, ceb, web and o eb have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). in addition the designer has to consider the minimu m inactivity time according to symbols 16, 17, 18, 19. for more information on the inactivity times (see figure 3) . 2. to allow proper internal initialization, after finishing any write access (ceb or web is high) to the internal controller_on register, ceb oeb and web have to be stable high within 200 ns (min = 8 tc). table 6. asynchronous dpram interface symbol parameter conditions min typ max units ceb web oeb 16 read read 18 write 17 write 19 read
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 12 - 20 AS8202NF ttp-c2nf data sheet - detailed description figure 4. write access timing (ceb controlled) figure 5. write access timing (web controlled) figure 6. read access timing (ceb controlled) figure 7. read access timing (oeb controlled) synchronous readyb generation figure 8. synchronous readyb timing synchronous readyb is aligned to host clock (with pulse dur ation of one host clock cycle) to fulfill the required host timing constraints for input setup and input hold time to/after host clock rising edge. note: connect use_ram_clk to v dd and ram_clk_testse to the host processor's bus clock to enable this mode of operation. due to possible metastability occurrence, it is not recommended to be used in safety critical systems. ceb web a valid valid d oeb readyb 1a 1b 2a 2b 3 6 5 4 ceb web a valid valid d oeb readyb 1a 1b 2a 2b 6 5 3 4 ceb web a valid d oeb readyb 7a 7b 8 11c 10 9 12 invalid valid 11a 11b ceb web a valid d oeb readyb 7a 7b 8 11c 10 9 12 invalid valid 11a 11b asynchronous readyb ram_clk_testse synchronous readyb 13 14 15
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 13 - 20 AS8202NF ttp-c2nf data sheet - detailed description reset and oscillator external reset signal to issue a reset of the chip the resetb port has to be driven low for at least 1 us. pulses under 50 ns duration are discarded. at power-up the reset must over lap the build-up time of the power supply. integrated power-on reset the device has an internal power-on reset generator. when supply voltage ramps up, the internal reset signal is kept active (low) for 33 s typical. note: in case of non-compliance keep the ex ternal reset (resetb) acti ve for min. 5 ms after supply voltage is valid and oscillator inputs active. oscillator circuitry the internal oscillators for main and bus guardian clock requ ire external quartzes or external oscillators. the main clock features a pll multiplying a 10 mhz xin0/xout0 osci llation to an internal frequency of 40 mhz when enabled. figure 9. main clock setup rf will normally not be soldered, it is onl y provided to get maximum flexibility. cext, typ = 15/18 pf. rd has to be calculat ed, if the measured drive level will be too high; if drive level is ok, rd = 0. table 7. pin mode pin name mode comment xin0 analog main oscillator input (external clock input) xout0 analog main oscillator output xin1 analog bus guardian oscillator input (external clock input) xout1 analog bus guardian oscillator output plloff in pll disable resetb in external reset table 8. parameters symbol parameter min typ max unit dv/dt supply voltage slope 551 - - v/ms tpores power on reset active time after v dd > 1,0v 25 33 49 s xin0 xout0 plloff vss 10 mhz rd rf cext cext xin0 xout0 plloff vss 10 mhz square wave xin0 xout0 plloff vdd 40 mhz square wave enabled pll, external quartz enabled pll, external oscillator disabled pll, external oscillator
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 14 - 20 AS8202NF ttp-c2nf data sheet - detailed description if using an external oscillator at 10 mhz with enabled internal pll, the oscillator must have a period of 100 ns with low jitter. note that a crystal-based clock is recommended over a derived clock (i.e., pll-based) to allow best internal pll performance. note: c load is the value of the external load capacitors to wards ground. the total load capacitance seen by the quartz will be c load _tot = (c load + cpar)/2. cpar is the equivalent parasitic capacitance of the oscillator cell inputs and the pcb and is derived from measurements to be about 3.5 ? 4.0 pf. figure 10. bus guardian clock setup both the xin0/xout0 (main clock) and the xin1/xout1 (b us guardian clock) cells support driving a quartz crystal oscillation as well as clock input by an external oscillator. build-up characteristics table 9. parameters parameter condition min typ max unit r_osc10 oscillation margin @ 10 mhz, c load = 18 pf 0.95 1 1. not tested during production. 1.62 1 k r_osc16 oscillation margin @ 16 mhz, c load = 18 pf 0.37 1 0.64 1 k r_osc20 oscillation margin @ 20 mhz, c load = 18 pf 0.24 1 0.41 1 k table 10. characteristics symbol pin parameter min typ max unit note tosc_startup0 xin0/ xout0 oscillator startup time (main clock) 20 ms quartz frequency: 10 mhz tosc_startup1 xin1/ xout1 oscillator startup time (bus guardian clock) 20 ms ms quartz frequency: 16 mhz tpll_startup0 xin0/ xout0 pll startup time (main clock) 20 ms ms quartz frequency: 10 mhz xin1 xout1 16 m hz rd rf cext cext xin1 xout1 16 m hz square wave external quartz external oscillator
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 15 - 20 AS8202NF ttp-c2nf data sheet - detailed description ttp bus interface the AS8202NF contains two ttp bus units, one for each ttp channel, building the ttp bus interface. each ttp bus channel contains a transmitter and a receiver and can be configured to be either in the asynchronous or synchronous mode of operation. note that the two channels (channel 0 and channel 1) can be configured independently for either of these modes. the drivers of the txd and cts pins are actively driven only during a transmission window, all the other time the drivers are switched off and the weak pull resistors are active . external pull resistors must be used to define the signal levels during idle phases. note: the transmission window may be different for each channel. ttp asynchronous bus interface when in asynchronous mode of operation the channel's bus unit uses a self-clocking transmission encoding which can be either mfm or manchester at a maximum data rate of 5 mbit/s on a shared media (physical bus). the pins can either be connected to drivers using recessive/dominant stat es on the wire as well as drivers using active push/pull functionality. the rxd signal uses '1' as the inactivity level. in the so-c alled rs485 compatible mode lon ger periods of '0' are treated as inactivity. if the rs485 compatible mode is not used, the app lication must care to drive rxd to '1' during inactivity on the bus. table 11. bus interface connections pin name tx inactive txd[0] weak pull-up cts[0] weak pull-down txd[1] weak pull-up cts[1] weak pull-down table 12. asynchronous bus interface connections pin name mode connect to phy note txd[0] out txd transmit data channel 0 cts[0] out cts transmit enable channel 0 txclk[0] in no function (do not connect) rxer[0] in no function (do not connect) rxclk[0] in no function (do not connect) rxdv[0] in no function (do not connect) rxd[0] in rxd receive data channel 0 txd[1] out txd transmit data channel 1 cts[1] out cts transmit enable channel 1 txclk[1] in no function (do not connect) rxer[1] in no function (do not connect) rxclk[1] in no function (do not connect) rxdv[1] in no function (do not connect) rxd[1] in rxd receive data channel 1
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 16 - 20 AS8202NF ttp-c2nf data sheet - detailed description ttp synchronous bus interface when in synchronous mode of operation, the bus unit uses a syn chronous transfer method to transfer data at a rate between 5 and 25 mbit/s. the interface is designed to run at 25 mbit/s and to be gluelessly compatible with the commercial 100 mbit/s ethernet mii (m edia independent inte rface) according to ieee standard 802.3 (ethernet csma/ cd). connecting the synchronous ttp bus unit to a 100 mbit/s ethernet phy is done by connecting txd, cts, txclk, rxer, rxclk, rxdv and rxd of any channel to txd0tx d0, txen, txclk, rxer, rxclk, rxdv and rxd0 of the phy's mii. the pins txd1, txd2 and txd3 of the phy's mii should be linked to v ss . the signals rxd1, rxd2, rxd3, col and crs as well as the mmii (managem ent interface) should be left open or can be used for diagnostic purposes by the application. note that the frames sent by the as82 02nf are not ethernet compatible and that an ethernet hub (not a switch) can be used as a 'star coupler' for proper operation. also not e that the ethernet phy must be configured for full duplex operation (even though the hub does not support full duplex), because ttp has its own collision management that should not interfere with the phy's half-duplex collision m anagement. in general, the phy must not be configured for automatic configuration ('auto negotiation') but be hard-configured for 100 mbit/s, full duplex operation. note: to run the interface at a rate other than 25 mbit /s other transceiver phy components have to be used. test interface the test interface supports the manufact uring test and characterization of the ch ip. in the application environment test pins have to be connected as following: stest, ftest, fidis: connect to v ss ttest: connect to v dd warning: any other connection of these pins may cause perm anent damage to the device and to additional devices of the application. table 13. synchronous bus interface connections pin name mode connect to phy note txd[0] out txd0txd0 transmit data channel 0 cts[0] out txen transmit enable channel 0 txclk[0] in txclk transmit clock channel 0 rxer[0] in rxer receive error channel 0 rxclk[0] in rxclk receive clock channel 0 rxdv[0] in rxdv receive data valid channel 0 rxd[0] in rxd0 receive data channel 0 txd[1] out txd0 transmit data channel 1 cts[1] out txen transmit enable channel 1 txclk[1] in txclk transmit clock channel 1 rxer[1] in rxer receive error channel 1 rxclk[1] in rxclk receive clock channel 1 rxdv[1] in rxdv receive data valid channel 1 rxd[1] in rxd0 receive data channel 1
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 17 - 20 AS8202NF ttp-c2nf data sheet - detailed description led signals the led port consists of three pins. vi a the medl each of these pins can be independently configured for any of the three modes of operation. at power-up and after reset the led port is inactive and only weak pull-down resistors are connected. after the controller is switc hed on by the host and when it is proce ssing its initialization, the led port is initialized to the selected mode of operation. each led pin can be configured to be either a push/pull dr iver (drives both low and high) or to be only an open- drain output (drives only low). table 14. led signals pin name protocol mode timing mode bus guardian mode led2 rpv 1 or protocol activity7 1. rpv is remote pin voting. rpv is a network-wide agreed signal used typically for agreed power-up or power- down of the application's external drivers. time overflow 2 2. time overflow is active for one clock cycle at the event of an overflow of the internal 16-bit time counter. time tick is active for one clock cycle when the internal time is counted up. time overflow and time tick can be used to externally clone the internal time control unit (tcu). with this information the application can precisely sample and trigger events, for example. action time 3 3. action time signals the start of a bus access cycle. led1 sync valid 4 4. the controller sets this output when cluster synchronization is achieved (after integration from the listen state, after acknowledge in the coldstart state). time tick 2 bde1 5 5. bde0 and bde1 show the bus guardian's activity, '1' signals an activated transmitter gate on the respective channel. led0 protocol activity 6 or rpv 7 6. protocol activity is typically connected to an optical le d. the flashing frequency and rhythm give a simple view to the internal ttp protocol state. 7. led2's rpv mode and led0's protocol activity mode can be swapped with a medl parameter. microtick 8 8. microtick is the internal main clock signal. bde0 5
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 18 - 20 AS8202NF ttp-c2nf data sheet - package drawings and markings 8 package drawings and markings the product is available in lqfp80 package. figure 11. package diagram note: 1. all dimensions are in millimeters, angle is in degrees. 2. dimensions d1 and e1 do not include mold protrusi on. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. dimensioning and tolerancing conform to jedec ms-026 rev a. 4. the top package body size may be smaller than the bottom body size by as much as 0.15 mm. table 15. package dimensions symbol min typ max symbol min typ max d 15.8 16 16.2 c1 0.09 0.16 d1 13.9 14 14.1 e 0.65 e 15.8 16 16.2 ccc 0.10 e1 13.9 14 14.1 ddd 0.13 b 0.22 0.32 0.38 n 80 b1 0.22 0.3 0.33 n/2 40 c 0.09 0.2 n/4 20
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 19 - 20 AS8202NF ttp-c2nf data sheet - ordering information 9 ordering information table 16. ordering information type marking description delivery form package AS8202NF-alqr AS8202NF ttp communication controller tray lqfp80 AS8202NF-alqt AS8202NF ttp communication controller tape&reel lqfp80 AS8202NF-alqu AS8202NF ttp communication controller tube lqfp80
www.austriamicrosystems.com and tttech computertechnik ag revision 2.1 20 - 20 AS8202NF ttp-c2nf data sheet - ordering information copyrights copyright ? 1997-200 9, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used wit hout the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freed om of the described devices from patent infringement. austriamicrosystems ag reserves the right to change spec ifications and prices at an y time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unus ual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to reci pient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact b

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